The present invention relates to a decision feedback equalizer of a high speed serial communication system, and more particularly, to clock recovery in a decision feedback equalizer.
In general, a decision feedback equalizer (hereinafter, which will be referred to as ‘DFE’ hereafter) plays a role of removing inter-symbol interference (hereinafter, which will be referred to as ‘ISI’ hereafter) due to high frequency channel loss in a high speed serial interface. The DFE removes interference components due to data that have been received previously and fed back from data received currently. Thus, equalization data is outputted to decide a value of the received data based on the equalization data. Such a DFE is used to remove the ISI generated in data inputted/outputted to/from a storage medium as well as the high speed serial interface between chips.
Meanwhile, feedback data of the DFE need to be fed back within a predetermined unit time, because, if the previous received data is not fed back within the predetermined unit time, edges between the current received data and the feedback data do not match, thereby causing another ISI in the equalization data. When the equalization data with the thus-caused ISI is inputted to a circuit for recovering a clock used for a feedback loop, the clock, which is gradually pushed backward, is recovered. That is, this makes a jitter of the recovered clock to increase. Furthermore, the delay in the feedback data increases in response to the clock, which is gradually pushed backward, thereby reducing the voltage margin of decided data.
Therefore, it is needed to prevent the increment of the jitter of the recovered clock due to the delay of the feedback data and reduction of the voltage margin of the decided data in the DFE.